Experience: 7+ Years

Technology Node: TSMC 3nm / 5nm (Mandatory)

Notice Period: Immediate Joiners / Maximum 30 Days

Domain: VLSI / Semiconductor

Job Location: Bengaluru / Hyderabad

Employment Type: Full-time

Job Overview

- We are looking for an experienced Senior Analog Layout Design Engineer with 7+ years of hands-on experience in full-custom analog and mixed-signal layout design.
- The candidate must have actual implementation experience in TSMC 3nm or 5nm technology nodes, with a strong understanding of advanced FinFET layout methodologies, complex analog block implementation and physical verification.
- The ideal candidate should be capable of independently handling complex analog layout blocks, driving layout optimization, resolving physical verification issues and collaborating closely with circuit design and physical verification teams.

Important: TSMC 3nm/5nm experience is mandatory. Candidates with experience only in other technology nodes will not be considered.

Key Responsibilities

- Analog / Custom Layout Design

- Lead and execute full-custom analog and mixed-signal layout implementation.
- Develop optimized layouts based on circuit schematics and design specifications.
- Handle floorplanning, device placement and routing of complex analog blocks.
- Implement matching-critical layouts using common-centroid, interdigitation and symmetry techniques.
- Ensure proper implementation of guard rings, shielding, isolation and well structures.
- Optimize layout for area, performance, power and signal integrity.
- Work closely with analog circuit designers to understand circuit requirements and layout constraints.

2. Advanced Technology Node Implementation
- Work on analog layout implementation using TSMC 3nm/5nm technology nodes.
- Apply advanced FinFET layout methodologies and technology-specific design rules.




- Understand advanced-node restrictions related to device placement, routing, density and patterning.
- Handle complex layout constraints associated with advanced technology nodes.
- Ensure compliance with TSMC PDK guidelines and foundry-specific layout requirements.

3. Physical Verification and Signoff
- Perform physical verification activities, including DRC, LVS and ERC.
- Debug and resolve complex physical verification violations.
- Work with Calibre or equivalent physical verification tools.
- Perform parasitic extraction and support post-layout verification.
- Ensure layout quality and signoff readiness.
- Coordinate with circuit design and physical verification teams for closure of layout-related issues.

4. Layout Optimization
- Optimize layouts to minimize parasitic capacitance, resistance and coupling effects.
- Implement appropriate shielding and routing strategies for sensitive analog signals.
- Ensure matching accuracy and minimize device mismatch.
- Optimize layouts for signal integrity, noise immunity and performance.
- Support EM/IR analysis and resolve layout-related reliability issues.

5. Technical Collaboration
- Collaborate with analog circuit design, physical verification and design teams.
- Review layout implementations and provide technical guidance to junior engineers.
- Participate in design reviews and technical discussions.




- Support project execution and ensure timely delivery of layout milestones.
- Drive layout quality and methodology improvements.

Required Technical Skills
- 7+ years of experience in Analog / Custom Layout Design.
- Mandatory hands-on experience in TSMC 3nm or 5nm technology nodes.
- Solid experience in full-custom analog and mixed-signal layout.
- In-depth understanding of FinFET technology and advanced-node layout methodologies.
- Proficiency in Cadence Virtuoso Layout Editor.
- Strong experience in DRC, LVS and ERC.
- Hands-on experience with Calibre or equivalent physical verification tools.
- Strong understanding of matching techniques, common-centroid, interdigitation and symmetry.
- Experience in parasitic minimization, shielding, guard rings and noise isolation.
- Ability to independently handle complex analog layout blocks.

Preferred Skills
- Experience in layout implementation of PLL, ADC, DAC, SERDES, LDO and high-speed analog blocks.
- Experience with advanced TSMC PDKs and foundry-specific design rules.
- Exposure to post-layout extraction and simulation.
- Knowledge of EM/IR analysis and signal integrity.
- Experience in mentoring junior engineers and reviewing layout deliverables.
- Exposure to other advanced technology nodes such as 7nm or below.

EDA Tools
- Cadence Virtuoso Layout Editor.
- Siemens Calibre.
- Cadence PVS / Pegasus.
- Cadence Quantus or equivalent parasitic extraction tools.

Education B.E./B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI or a related discipline.

Notice Period Requirement

- Immediate joiners preferred.
- Candidates serving notice period with a confirmed last working day within 30 days.
- Maximum acceptable notice period: 30 days.
- Candidates with notice periods exceeding 30 days will not be considered.

📌 Senior Analog Layout Design Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru