RTL Design Engineer (Chip-Level Integration)

Company: CoreIC Technologies

Location: Bangalore

Experience: 3+ years

About the Role

We’re looking for an RTL Design Engineer to work on chip-level integration of complex SoCs. You’ll integrate and connect IPs and subsystems, and make sure the design is clean, verified and ready for downstream implementation.

Key Responsibilities

Perform chip-level and subsystem-level RTL integration

Integrate IPs using standard interfaces and protocols such as Ethernet, PCIe, AXI and SPI

Write and review RTL in Verilog/SystemVerilog

Run lint checks and fix violations

Run CDC analysis and resolve clock domain crossing issues

Work with verification, DFT, physical design and architecture teams to close issues

Debug integration issues and support simulation and bring-up

Required Skills

3+ years of hands-on experience in chip-level integration





Robust working knowledge of Verilog

Good understanding of protocols: Ethernet, PCIe, AXI, SPI, etc.

Practical experience with Lint and CDC tools and methodologies

Solid understanding of digital design fundamentals and clocking/reset architecture

Good debugging and communication skills

Good to Have

Experience with SystemVerilog and scripting (Python/Perl/TCL)

Exposure to synthesis, SDC constraints and timing concepts

Experience with DDR or other high-speed interfaces

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electronics & Communication, or a related field

How to Apply

Best Regards

Vibhuti Prajapati

Associate Director -TA [email protected]

📌 RTL Design Engineer (Chip-Level Integration) (Bengaluru)
🏢 CoreIC Technologies
📍 Bengaluru