Own the front-end RTL of a microcontroller SoC — the micro-architecture, the finite state machines and datapath, the FIFOs and the clock-domain crossings, the AMBA bus fabric and the peripheral interfaces (UART, SPI, I²C, QSPI, USB) that connect the CPU, memory and the outside world. A front-end role: spec to a clean, verified netlist handed to the back-end team.

What the role involves.

- Define the micro-architecture of a microcontroller SoC — block partitioning, datapath, memory map and the register interface — and turn it into RTL.
- Write synthesisable Verilog and SystemVerilog: finite state machines, FIFOs, arbiters, counters and the control logic that actually runs the chip.




- Design the clocking and reset architecture and the clock-domain crossings — the synchronisers and FIFOs that make multi-domain logic protected.
- Integrate the CPU subsystem (Arm Cortex-M or RISC-V) and the AMBA (AHB/APB) bus fabric, with the memory, interrupt and DMA controllers around it.
- Design the peripheral blocks to their protocol specifications and corner cases — UART, SPI, I²C, QSPI/OSPI flash, USB, CAN-FD, timers/PWM and GPIO.
- Keep lint and CDC clean as a condition of check-in, and work alongside verification so coverage closes against the spec rather than after it.
- Lead a small front-end team and own the RTL deliverable the synthesis, DFT and physical-design teams build from.

📌 Principal RTL Designer — Microcontrollers (MCU) (Bengaluru)
🏢 FASTSTREAM TECHNOLOGIES
📍 Bengaluru