About the Role

This role is for a Memory Layout Engineer with 3-7 years of experience to design and develop memory blocks for integrated circuits (ICs). You will be responsible for creating efficient memory layouts that meet performance, power, and area constraints.

Responsibilities

- Design memory layouts for various building blocks including:

Bit cell array

Row decoder

Column decoder

Sense amplifiers

Input/Output (I/O) blocks

Integrate top-level memory blocks
- Perform physical verification using tools like Design Rule Check (DRC) and Layout Versus Schematic (LVS)
- Ensure layouts meet Design for Manufacturability (DFM) and Design for Yield (DFY) requirements
- Analyze layouts for potential power and signal integrity issues
- May involve scripting using languages like PERL, Shell, TCL, or Skill

Qualifications

- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 3-5 years of experience in memory layout design
- Proven experience with memory layout tools like Cadence Virtuoso and Assura
- Understanding of memory compiler architectures and sub-blocks
- Experience with low-power, high-performance,



and high-density SRAM memory design (experience with different technology nodes is a plus)
- Knowledge of Design for Manufacturability (DFM) and Design for Yield (DFY) concepts
- Strong analytical and problem-solving skills
- Excellent communication and teamwork abilities

Required Skills

- Proven experience with memory layout tools like Cadence Virtuoso and Assura
- Understanding of memory compiler architectures and sub-blocks
- Experience with low-power, high-performance, and high-density SRAM memory design (experience with different technology nodes is a plus)
- Knowledge of Design for Manufacturability (DFM) and Design for Yield (DFY) concepts
- Robust analytical and problem-solving skills
- Excellent communication and teamwork abilities
- May involve scripting using languages like PERL, Shell, TCL, or Skill

Preferred Skills

- Experience with custom and compiler-based memory layout
- Experience with FinFET process technologies
- Experience with memory verification methodologies

📌 Memory Layout Engineer (Bengaluru)
🏢 HCLTech
📍 Bengaluru