We are looking for a skilled Memory Layout Engineer with 3+ years of experience in custom layout design and implementation of memory circuits. The candidate should have solid knowledge of SRAM/DRAM layout, layout verification, physical verification, and semiconductor design methodologies.
Required Skills
- 3+ years of experience in Memory Layout Design.
- Strong knowledge of SRAM/DRAM layout design.
- Experience in FinFET technology and Lower Nodes
- Experience in custom analog layout design.
- Good understanding of CMOS fundamentals and semiconductor fabrication processes.
- Hands-on experience with DRC, LVS, and PEX.
- Knowledge of memory architecture, bit cells, sense amplifiers, and peripheral circuits.
- Experience with Cadence Virtuoso and physical verification tools such as Calibre or equivalent.
- Good debugging and problem-solving skills.