At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Formal Verification Architect, PCIe & UALink Controllers Role Summary We are looking for an experienced Formal Verification Architect to lead the formal verification strategy for high-performance PCIe and UALink controller IP. The ideal candidate will combine deep formal verification expertise with robust protocol and microarchitecture knowledge. This is a hands-on technical leadership role responsible for defining verification architecture, identifying high-value formal targets, solving complex proof problems, and driving formal methods throughout the IP development lifecycle.

Key Responsibilities
• Define the formal verification architecture and methodology for PCIe and UALink controller IP.
• Develop block, subsystem, and end-to-end formal verification strategies spanning:
• Protocol engines and state machines
• Transaction and packet processing
• Flow control and credit management
• Ordering and dependency rules
• Replay, retry, recovery, and error handling
• Arbitration, scheduling, and resource management
• Power/reset and initialization sequences
• Configuration and control logic
• Identify areas where formal verification can provide stronger coverage than simulation, especially for corner cases, deadlocks, livelocks, starvation, ordering violations, data integrity, and protocol compliance.
• Architect assume-guarantee, compositional, abstraction, and formal decomposition strategies for large and complex controller designs.
• Develop reusable SystemVerilog Assertions (SVA), properties, checkers, constraints, and formal verification IP.
• Drive convergence of difficult proofs through abstraction, cut-points, state-space reduction, invariants, partitioning,



and proof-debug techniques.
• Work closely with RTL architects and designers to improve design-for-formal-verification and resolve architectural ambiguities early.
• Define formal coverage criteria and establish metrics for proof completeness, unreachable states, vacuity, assumptions, and coverage closure.
• Lead formal analysis of complex bug classes that are difficult to expose through constrained-random simulation.
• Establish the appropriate balance between formal, simulation, emulation, and system-level verification.
• Review verification plans and architecture specifications to identify formal opportunities and verification gaps.
• Mentor verification engineers and raise formal verification capability across the broader controller verification organization. Required Qualifications
• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Typically 15+ years of Verification experience, with significant hands-on formal verification experience of 5 years at least.
• Deep expertise in property-based formal verification of complex RTL.
• Deep knowledge of PCI Express, preferably PCIe 5.0/6.0/7.0 controller architecture and verification.
• Experience with UALink, CXL, UCIe, Ethernet, or comparable high-performance interconnect protocols
• Strong knowledge of:
• SystemVerilog and SVA
• Formal property development
• Assumption and constraint modeling
• Abstraction and decomposition
• Formal coverage and proof closure
• Counterexample analysis and debug
• Hands-on experience with industry formal platforms such as Cadence Jasper or Equivalent
• Experience applying formal verification to high-speed interconnect or networking controller designs. We’re doing work that matters. Help us solve what others can’t.

📌 Design Verification Architect (Bengaluru)
🏢 Cadence Design Systems
📍 Bengaluru