Technical Architect-Physical Design

Location:
Bengaluru

Experience:
12–18 Years Role Overview: We are looking for a highly experienced Technical Architect – Physical Design to drive full-chip physical design architecture, implementation strategy and technical execution for complex SoC designs. The ideal candidate should possess deep expertise in full-chip physical design, Cadence Innovus and Static Timing Analysis (STA), with the ability to drive architectural decisions, PPA optimization and end-to-end design closure.

Key Responsibilities
• Define and drive physical design architecture and implementation strategies for complex full-chip SoC designs.
• Own end-to-end physical design execution from floorplanning through placement, CTS, routing and final signoff.
• Drive full-chip timing closure, STA analysis and optimization across multiple operating corners and modes.
• Define floorplanning, partitioning, power planning and hierarchical implementation strategies.
• Lead PPA optimization initiatives covering performance, power and area.
• Drive timing convergence, congestion optimization and signal integrity considerations.
• Establish physical design methodologies, implementation flows and design quality standards.
• Provide technical direction and architectural guidance to physical design teams.
• Collaborate with RTL, DFT, STA, synthesis and physical verification teams.




• Identify critical design risks and drive technical solutions for complex implementation challenges.
• Review implementation strategies, signoff reports and design quality metrics.
• Drive technical reviews, methodology improvements and engineering best practices. Required Technical Skills
• 12–18 years of experience in ASIC/SoC Physical Design.
• Extensive experience in Full-Chip Physical Design implementation.
• Strong hands-on expertise in Cadence Innovus.
• Deep understanding of Static Timing Analysis (STA) and timing closure.
• Expertise in floorplanning, placement, CTS, routing and physical optimization.
• Strong understanding of timing constraints, multi-mode multi-corner (MMMC) analysis and optimization.
• Experience in full-chip PPA optimization and convergence.
• Strong understanding of hierarchical and flat physical design methodologies.
• Experience in complex SoC implementation and signoff closure.
• Ability to provide technical leadership and drive design architecture decisions. Preferred Qualifications
• BE/BTech/MTech in Electronics, Electrical or VLSI-related disciplines.
• Experience with advanced semiconductor technology nodes.
• Robust exposure to large-scale SoC physical design architecture.
• Experience in developing and optimizing physical design methodologies.
• Proven ability to solve complex timing and implementation challenges.

📌 Technical Architect-Physical Design (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru