SoC Verification Lead 8–12 years

Key Responsibilities
• Define, develop, and execute comprehensive verification plans and strategies for IP and SoC-level designs.
• Architect and develop scalable, reusable C & UVM/SystemVerilog-based verification environments from scratch.
• Lead testbench architecture and implementation, including stimulus generation, scoreboards, assertions, functional coverage, and verification infrastructure.
• Drive verification closure through coverage analysis, regression management, bug tracking, and verification sign-off.
• Collaborate closely with RTL design, architecture, and firmware teams to debug and resolve functional issues and achieve verification milestones.
• Perform complex debugging across RTL simulation, gate-level simulation, and emulation/prototyping platforms.
• Mentor junior engineers, provide technical guidance, and drive improvements in verification methodologies, automation, and overall productivity. Qualifications & required technical skills
• BE/B.
Tech/ME/M.
Tech (or equivalent) in ECE/EEE/CSE.
• 8–12 years of hands-on experience in IP
- and SoC-level functional verification, including verification planning, testbench development, and verification closure.
• Solid understanding of processor-based SoC architectures, with working knowledge of ARM and/or RISC-V CPU subsystems.
• Strong programming skills in C and SystemVerilog, with expertise in UVM and SystemVerilog Assertions (SVA).
• Hands-on verification experience with one or more high-speed interfaces or protocols, such as:
• PCIe / CXL
• AMBA (AXI, AHB, APB, ACE / CHI)
• Ethernet
• USB
• DDR / LPDDR
• Experience in integrating, configuring, and customizing commercial Verification IP (VIP).
• Proficiency in RTL debugging and simulation using industry-standard EDA tools, particularly Synopsys VCS.
• Strong understanding of constrained-random verification, coverage-driven verification,



and functional coverage closure.
• Proven ability to independently debug complex design and verification issues and drive them to resolution. Preferred/Positive-to-Have Skills
• Experience with low-power verification methodologies, including UPF / CPF.
• Exposure to gate-level simulation, emulation, and FPGA-based prototyping.
• Familiarity with scripting languages such as Python, Perl, or Tcl for verification automation.
• Experience in developing and improving verification methodologies, infrastructure, and regression efficiency.
• Strong problem-solving, communication, and mentoring skills. Why Join Us?
• Lead verification for complex, high-performance SoCs with broad ownership from planning to tape-out signoff.
• Work at the core of SEMIFIVE’s platform-driven silicon approach, enabling reuse and scalable methodologies.
• Collaborate with world-class, cross-functional teams across architecture, design, DFT, and Integration.
• Grow as a technical leader by mentoring engineers and driving automation and best practices.
• Be part of a rapidly scaling India design centre delivering first-time-right silicon for global customers. About Semifive Founded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea’s semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end to back-end design, SEMIFIVE has become the fastest growing silicon design company that offers the most comprehensive design solutions. SEMIFIVE’s core business is its innovative SoC Platform that enables low-cost and high-efficiency SoC design and also provides full turnkey silicon design services for global customers. Semifive India Design Centre, headquartered in Bangalore, is a rapidly growing capability centre responsible for delivering complex, multi-node SoC programs for global customers across the US, Europe, and Asia. The India team owns front-end through back-end execution, including RTL, STA, synthesis, physical design, and signoff for turnkey silicon programs.

📌 Verification Lead (Bengaluru)
🏢 SEMIFIVE
📍 Bengaluru