Experience:
3+ Years Domain: VLSI / Semiconductor Job

Location:
Bengaluru / Hyderabad / Noida Employment Type: Full-time Job Overview We are looking for a skilled Memory Circuit Design Engineer with 3+ years of experience in transistor-level circuit design and development of memory circuits. The ideal candidate should have hands-on experience in SRAM/DRAM circuit design, memory peripheral circuits, SPICE simulations and circuit optimization across different PVT corners.

Key Responsibilities
• Design, develop and optimize transistor-level circuits for memory architectures such as SRAM, DRAM, ROM and Register Files.
• Work on memory bitcell design and optimization, including 6T/8T SRAM bitcells.
• Design and develop memory peripheral circuits such as:
• Sense Amplifiers
• Write Drivers
• Pre-charge Circuits
• Row and Column Decoders
• Wordline Drivers
• Address and Data Path Circuits
• Perform transistor-level simulations using SPICE-based simulators.
• Conduct functional, timing, power and performance analysis of memory circuits.
• Perform PVT corner simulations and Monte Carlo analysis.
• Analyze and optimize memory access time, leakage power, dynamic power and stability.
• Work on SRAM stability analysis, including SNM (Static Noise Margin), read/write margin and bitcell robustness.
• Collaborate with layout,



verification and physical design teams for successful memory IP development.
• Debug circuit-level issues and ensure compliance with design specifications. Required Technical Skills
• 3+ years of experience in Analog/Mixed-Signal or Memory Circuit Design.
• Strong fundamentals in CMOS transistor-level circuit design.
• Hands-on experience in SRAM/DRAM circuit design or memory peripheral circuit development.
• Valuable understanding of SRAM architecture and memory operations.
• Experience with SPICE-based simulation tools such as Spectre, HSPICE, FineSim, PrimeSim or SpectreFX.
• Experience in PVT, Monte Carlo and transient/DC/AC simulations.
• Understanding of timing, power, noise, stability and circuit optimization.
• Knowledge of CMOS process technologies and device characteristics. Preferred Skills
• Experience in 6T/8T SRAM bitcell design and optimization.
• Experience in sense amplifier and write driver design.
• Knowledge of DRAM architecture and memory timing.
• Exposure to advanced technology nodes (28nm, 16nm, 7nm, 5nm or below).
• Experience with Cadence Virtuoso and Spectre.
• Knowledge of memory characterization and silicon validation.
• Understanding of memory layout constraints and parasitic effects. Education B.
E./B.
Tech/M.
Tech in Electronics, Electrical Engineering, VLSI or a related discipline.

📌 Memory Circuit Design Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru