Experience:
4+ Years Technology Node: TSMC 3nm / 5nm (Mandatory) Domain: Semiconductor / VLSI Job

Location:
Bengaluru / Hyderabad Employment Type: Full-time Job Overview We are looking for an experienced Analog Layout Engineer with 4+ years of hands-on experience in custom analog layout design, specifically on TSMC 3nm or 5nm technology nodes. The ideal candidate should have solid expertise in full-custom analog layout, advanced FinFET technology, physical verification and layout optimization. Experience working on complex analog/mixed-signal blocks and advanced-node design methodologies is essential.

Key Responsibilities
• Develop full-custom analog and mixed-signal layouts for advanced semiconductor designs.
• Work on analog layout implementation using TSMC 3nm/5nm technology nodes.
• Handle floorplanning, placement and routing of analog/mixed-signal circuit blocks.
• Implement matching-critical layouts using common-centroid, interdigitation and symmetry techniques.
• Perform layout optimization for area, performance, power and signal integrity.
• Ensure proper implementation of guard rings, shielding, well structures and isolation techniques.
• Perform physical verification activities, including DRC, LVS and ERC.
• Debug and resolve physical verification violations in accordance with foundry design rules.
• Work closely with analog circuit design, physical verification and technology teams.
• Analyze and minimize parasitic effects,



coupling and substrate noise.
• Ensure layout compliance with advanced FinFET technology design constraints. Required Technical Skills
• 4+ years of experience in Analog / Custom Layout Design.
• Mandatory hands-on experience with TSMC 3nm or 5nm technology nodes.
• Strong understanding of FinFET technology and advanced-node layout methodologies.
• Hands-on experience with full-custom analog layout design.
• Proficiency in Cadence Virtuoso Layout Editor.
• Strong experience in physical verification – DRC, LVS and ERC.
• Experience with Calibre or equivalent physical verification tools.
• Good understanding of matching techniques, shielding, guard rings and parasitic minimization.
• Ability to interpret circuit schematics and translate them into optimized layouts.
• Understanding of analog/mixed-signal layout constraints and foundry-specific design rules. Preferred Skills
• Experience with analog/mixed-signal blocks such as PLL, ADC, DAC, SERDES, LDO and high-speed interfaces.
• Experience in advanced FinFET nodes and associated layout restrictions.
• Exposure to EM/IR analysis and parasitic extraction.
• Experience with TSMC process design kits (PDKs).
• Knowledge of advanced-node physical verification and debugging methodologies. Education B.
E./B.
Tech/M.
Tech in Electronics, Electrical Engineering, VLSI or a related discipline.

📌 Analog Layout Engineer (Hyderabad)
🏢 leadIC Design
📍 Hyderabad