Experience:
4–6 Years Domain: VLSI / Semiconductor / ASIC Design Job

Location:
Bengaluru Employment Type: Full-time Job Overview We are looking for an experienced RTL Design Engineer with 4–6 years of experience in digital design and RTL development for complex ASIC/SoC designs. The ideal candidate should have robust expertise in RTL coding using Verilog/SystemVerilog, digital design fundamentals, microarchitecture implementation, synthesis and design debugging. The candidate will be responsible for developing high-quality, synthesizable RTL, implementing design specifications and collaborating with architecture, verification and physical design teams throughout the ASIC development lifecycle.

Key Responsibilities
1. RTL Design and Development
• Develop, implement and maintain synthesizable RTL using Verilog and SystemVerilog.
• Translate microarchitecture specifications and design requirements into efficient RTL implementations.
• Design and implement digital blocks such as FSMs, counters, FIFOs, arbiters, pipelines, registers and control logic.
• Develop optimized RTL for performance, power and area requirements.
• Ensure RTL coding quality, readability, reusability and adherence to coding guidelines.
• Perform RTL modifications and enhancements based on design requirements. 2. Microarchitecture and Digital Design
• Understand and analyze microarchitecture specifications.
• Participate in design discussions and contribute to microarchitecture development.
• Implement datapath and control logic for complex digital subsystems.
• Work on pipelining, clock domain crossing and reset synchronization.
• Handle design complexity involving multiple clock domains and high-speed interfaces.




• Ensure proper implementation of timing-sensitive logic. 3. RTL Debugging and Validation
• Perform RTL simulations and debug functional issues.
• Analyze simulation failures and resolve RTL-related bugs.
• Work closely with verification engineers to resolve design issues.
• Support functional verification, coverage closure and design validation.
• Review RTL code and participate in design reviews.
• Ensure RTL implementation matches architectural and functional specifications. 4. Synthesis and Design Optimization
• Perform RTL synthesis and analyze synthesis reports.
• Understand timing, area and power implications of RTL coding styles.
• Optimize RTL for improved PPA (Power, Performance and Area).
• Analyze critical paths and address RTL-level timing bottlenecks.
• Resolve synthesis warnings and coding-related issues.
• Support synthesis and physical design teams during implementation. 5. Design Quality and Integration
• Perform lint analysis and resolve RTL coding violations.
• Ensure proper clocking, reset and CDC methodologies.
• Collaborate with DFT, verification, synthesis and physical design teams.
• Support subsystem integration and top-level RTL integration.
• Maintain design documentation and technical specifications. Required Technical Skills




• 4–6 years of hands-on experience in RTL Design and Development.
• Strong proficiency in Verilog and SystemVerilog.
• Strong understanding of digital design fundamentals and computer architecture.
• Experience in synthesizable RTL coding.
• Good understanding of FSM, FIFO, counters, arbiters, pipelines and datapath design.
• Experience with RTL simulation and debugging.
• Understanding of synthesis concepts and optimization techniques.
• Knowledge of timing constraints and static timing analysis fundamentals.
• Experience with lint tools and RTL quality checks.
• Understanding of clock domain crossing (CDC) and reset domain crossing (RDC).
• Ability to interpret microarchitecture specifications and implement RTL accordingly. EDA Tools Hands-on experience with one or more of the following tools:
• Simulation: Synopsys VCS, Cadence Xcelium, QuestaSim.
• Synthesis: Synopsys Design Compiler, Cadence Genus.
• Lint: SpyGlass, Questa Lint.
• CDC: SpyGlass CDC, Questa CDC.
• Debug: Verdi, SimVision. Preferred Skills
• Experience in ASIC/SoC development.
• Exposure to advanced technology nodes (16nm, 7nm, 5nm or below).
• Understanding of AMBA protocols such as AXI, AHB and APB.
• Exposure to high-speed interfaces such as PCIe, USB, DDR or Ethernet.
• Knowledge of low-power design methodologies and UPF.
• Understanding of DFT concepts and scan design.
• Experience with Tcl, Python or Perl scripting.
• Exposure to formal verification and equivalence checking. Education B.
E./B.
Tech/M.
Tech in Electronics, Electrical Engineering, VLSI or a related d

📌 RTL Design Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru