Location:
Hyderabad Notice Period: Immediate to 15 Days only Mandatory Skills
• Strong experience in Design Verification (DV)
• Hands-on experience in Gate-Level Simulation (GLS)
• Solid knowledge of Verilog and System Verilog
• Experience in simulation, debugging, and failure analysis
• Good understanding of timing concepts and SDF annotation
• Strong debugging and problem-solving skills
• Min 3 projects in GLS