Company Description Sykatiya Technologies Pvt Ltd is a VLSI design and test services company, delivering quality and timely solutions across the semiconductor design lifecycle. The organization provides full turnkey production-ready designs, subsystem and IP block development, and specialist engineering support to augment customer design teams. Its multidisciplinary team includes experienced engineers in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs, with a strong focus on technical excellence and collaborative attitude. Sykatiya Technologies specializes in disruptive ultra-low-power optimization technologies, helping clients achieve or surpass power and area targets beyond standard flows. The company partners closely with technology providers to bring advanced RTL-to-GDS low-power engineering solutions to global customers. Role Description The Senior Physical Design Engineer will work on-site in Bangalore in a full-time capacity, contributing to complex ASIC and SoC implementations from RTL to GDSII. Responsibilities include floorplanning, placement, clock tree synthesis, routing, and timing closure, while optimizing for power, performance, and area. The role involves collaborating with RTL, verification, and DFT teams to ensure robust integration and sign-off, as well as driving physical verification and resolving design and layout issues. The engineer will analyze and improve low-power strategies, participate in design reviews, and support tape-out activities.



This position also requires mentoring junior engineers, sharing best practices, and contributing to continuous flow and methodology improvements. Qualifications
• Candidates must have 6-15yrs experience and possess strong skills in Physical Design, including floorplanning, placement, CTS, routing, timing closure, and power/area optimization.
• Candidates should possess skills in Physical Verification, such as DRC, LVS, EM/IR analysis, and sign-off using industry-standard EDA tools.
• Candidates should possess skills in Logic Design and RTL Design, enabling effective collaboration with front-end teams and understanding of synthesis and timing constraints.
• Candidates should possess skills in Circuit Design, including understanding of standard cells, clocking schemes, and power distribution networks.
• Hands-on experience with major EDA tool suites for implementation and verification (e.g., Cadence, Synopsys, Siemens) is highly beneficial.
• A robust background in low-power design techniques and experience with advanced process nodes is preferred.
• Excellent analytical, problem-solving, and communication skills, with the ability to work collaboratively in cross-functional engineering teams.
• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field, with several years of relevant industry experience in physical design.

📌 Senior Physical Design Engineer (Hyderabad)
🏢 Sykatiya Technologies
📍 Hyderabad