Date: 15.04.2025 - ad hoc basis in the project 1. Name of post Senior Project Associate Engineer 2. Job Description Software/hardware design expert with B. Tech or M. Tech with an experience of - 2-3 year’s. The tasks performed are development of design and algorithms. Also, - development of system-level-simulation tools and development of RTL on FPGA - boards and embedded software. 3. No. of post 02 4. Essential - Qualification B tech / BE/ M tech /MCA/MSC/BSC ME / MS Master’s Bachelor’s degree - Electrical /Electronic engineering, Computer engineering or Equivalent practical - experience 5. Skills - /Experience - Required - Exp Level 2 to 3 Years - Domian Knowledge on RTL Design, implementation, and integrations for FPGA Designs. - Knowledge with RTL coding using Verilog/System Verilog. - Experience with protocols like AXI4-stream and AXI4.



- Robust debugging capabilities at RTL simulation and FPGA Emulation. 6. Consolidated - Pay Rs. 100,000 to 121,000 7. Anticipated start - date 01st June 2025 8. Tenure of - employment - subsequent terms based on his/her performance and requirement of the - Department/Institute. 9. Mode of - selection Test and interview 10. Selection - Procedure /Mode - 66ApcUQ/edit - record, and relevant experience and selected based on the performance is the - Witten interview. - 4 IIT Hyderabad reserves the right to alter the number of vacancies or keep it - open till the deserving the right to close the recruitment procedure with out 11. Tentative date - of interview

📌 Advertisement for Senior Project Associate Engineer, Iit Hyderabad (Kandi)
🏢 Indian Institute of Technology Hyderabad
📍 Kandi