Bangalore, Karnataka

Job Summary

Good understanding of ASIC/SoC life cycle

Has participated in multiple ASIC/SoC verification till tapeout stage

Experience writing ASIC/SoC testplans

.Experience in ASIC/SoC Testbench definitionExperience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."

Experience in developing TB components for SOC with C, SV

Expertise & hands-on experience in OVM/UVM methodologies using SV

Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans."

Experience in developing TB components, including functional coverage implementation and assertion coding

Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.

Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.

Experience in SOC C based tests coding & debugging.

Experience 5 to 10 year.

Key Responsibilities

Experience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files.

Experience in Collaborating closely with the hardware design team to analyze, document, and resolve bug reports efficiently.

Experience in Document test plans, micro-architecture specifications, and verification results for team reviews

Experience to lead the micro-architecture and full-chip verification of our next-generation semiconductor products

End-to-end ownership of complex IPs and subsystems, from defining functional specifications to managing final tape-out sign-off. You will architect robust, scalable UVM environments, solve critical architectural bottlenecks, and mentor a team of engineers to ensure first-pass silicon success

Develop complex verification components,



including bus functional models (BFMs), monitors, predictors, and highly parameterized scoreboards.

Oversee and resolve deep technical issues in Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), linting, and formal verification.

Direct the deployment of advanced verification techniques such as Formal Verification, Hardware Emulation (e.g., Palladium, Zebu), and Power-Aware (UPF/CPF) simulations.

Act as the primary technical point of contact, interfacing with System Architects, Backend/Physical Design teams, and Post-Silicon Validation teams.

Provide technical mentorship, code reviews, and career guidance to junior and mid-level design and verification engineers.

Establish, standardize, and continuously improve engineering methodologies, automation scripts, and best practices across the organization.

Bachelor's or Master's degree in Electronics & Communication Engineering (ECE),

Electrical Engineering (EE), VLSI Design, or a closely related field"

Skill Requirements

Tools : Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms.

"Protocols : Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)."

Other Requirements

Scripting : Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking. Strategic Thinking : Ability to foresee technical risks weeks or months in advance and proactively implement mitigation strategies. Influence : Solid leadership and communication skills to guide cross-functional teams and align stakeholders on technical directions.

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📌 Senior Design Lead - Design Validation (Bengaluru)
🏢 HCLTech
📍 Bengaluru