Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, adaptable systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Tech Lead STA Engineer
Experience - 6-14 years

Astera Labs is hiring a Principal Engineer, Static Timing Analysis to own top-level timing closure and signoff for our next-generation connectivity silicon powering rack-scale AI infrastructure. In this role, you'll drive full-chip STA strategy across advanced process nodes, partner with physical design, RTL, DFT, and CAD teams, and ensure first-pass timing success on some of the most complex SoCs in the industry.
This is a high-impact technical leadership role at a hyper-growth company purpose-built for AI connectivity.



Full-Chip STA Signoff & Timing Closure
Own end-to-end top-level STA signoff across multiple modes, corners, and operating conditions (MMMC) for complex AI connectivity SoCs
Partner with Physical Design, RTL, DFT, CAD, and Package teams to drive timing-aware design decisions from architecture through tapeout
Bachelor's degree in Electrical Engineering, Electronics Engineering, or related field

- 6+ years of hands-on experience in Static Timing Analysis on complex ASIC/SoC designs
- Proven track record of full-chip top-level STA signoff on at least one tapeout at advanced nodes (7nm or below)
- Proficiency in scripting (Tcl, Python, Perl) for STA flow automation and report analysis

Master's degree in Electrical Engineering or related field
Experience with high-speed connectivity SoCs (PCIe Gen 6/7, CXL, UALink, or Ethernet)
Experience with low-power signoff (UPF/CPF), multi-voltage domains, and DVFS timing implications
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

📌 Python Tech Lead (Secunderabad)
🏢 Astera Labs
📍 Secunderabad