About the Company
www.enchargeai.com

About the Role
Locations: Bangalore (Hybrid-2 days office/3 days Home)/ Remote ( Any where in India ) Security Architect – Datacenter-Scale AI Inference

Location:
Onsite/hybrid/Remote

Job Description
EnCharge AI is seeking an experienced Security Architect with a strong background in hardware and platform security to define the security architecture of our next-generation datacenter-scale AI inference systems. You will own security from the accelerator silicon out to the server, rack, and cluster, spanning scale-up and scale-out fabrics as well as the host and management planes, ensuring robustness from power-on to runtime in a virtualized, multi-tenant deployment where model weights and customer data must stay protected end to end. This role focuses on designing and integrating security features such as platform Root of Trust (RoT), secure and measured boot, device attestation, confidential computing, link and memory encryption, and key lifecycle management across the accelerator, host CPU, NIC/DPU, and BMC. You will define and drive architectural specifications for trusted I/O over PCIe, encrypted scale-up and scale-out interconnects, and isolation mechanisms at the hardware, firmware, and system-software layers, and work with silicon, systems, firmware, and operations teams to turn them into a product that ships, scales, and certifies. Responsibilities
• Own the end-to-end security architecture and threat model for the inference platform (accelerator SoC, card, server node, rack, and cluster), covering remote, physical, supply-chain, malicious-tenant, and malicious-operator adversaries.
• Define the platform chain of trust: secure and measured boot across accelerator, host, NIC/DPU, and BMC, anchored in a hardware RoT (e.g., Caliptra or a discrete platform RoT), with anti-rollback, resilience, and recovery per NIST SP 800-193.
• Architect device identity and attestation using DICE and SPDM, including certificate provisioning in manufacturing, runtime measurement reporting, and integration with fleet attestation and verification services.
• Define confidential computing support for AI workloads:



integration with host CPU TEEs (Intel TDX, AMD SEV-SNP, Arm CCA), TDISP/TEE-IO, PCIe/CXL IDE, and encrypted HBM/DRAM, so tenant models and data remain protected from the host, hypervisor, and operator.
• Architect protection of model weights and tenant data in multi-tenant inference: isolation across partitions and virtual functions, DMA protection, memory and KV-cache scrubbing between tenants, and encrypted model loading with key release gated on attestation.
• Specify link encryption and authentication for scale-up fabrics (NVLink/UALink-style) and scale-out networks (Ethernet/Ultra Ethernet with MACsec, IPsec, or PSP), balancing line-rate throughput, latency, area, power, and key-rotation requirements with the interconnect and performance teams.
• Define the key management architecture: on-die key hierarchy, derivation and rotation, fuse/OTP provisioning, and integration with external KMS/HSM services for key wrapping and release.
• Own secure firmware update and supply-chain integrity for every platform component: signed, versioned images, code-signing infrastructure requirements, SBOMs, and secure manufacturing and provisioning flows.
• Architect SoC-level and IP-level protections, including secure debug and lifecycle states, security monitors/sensors, and countermeasures against side-channel and fault-injection attacks.
• Define and develop the security verification and validation plan with pre-silicon (simulation, formal, emulation) and post-silicon teams, and drive internal and third-party penetration testing and design reviews.
• Drive compliance and certification readiness (e.g., FIPS 140-3, Common Criteria, OCP S.
A.
F.
E. firmware reviews) and track and contribute to relevant standards bodies (OCP, DMTF, PCI-SIG, TCG, UEC, Confidential Computing Consortium).




• Serve as the senior technical authority on security across the architecture organization: set direction across product generations, mentor architects and engineers, and lead customer and partner security reviews.
• Collaborate with silicon, firmware, system software, and cloud operations teams to ensure secure HW/SW co-design, and participate in silicon and system bring-up of secure features. Qualifications
• BS/MS/Ph.
D. in EE, CE, CS, or related field with 10+ years of experience in hardware, SoC, or platform security architecture, including technical leadership of security for at least one shipped silicon or server product. Required Skills
• Solid knowledge of hardware security architecture: roots of trust, secure and measured boot, key provisioning, crypto engines, and secure debug/test interfaces.
• Hands-on experience with attestation and platform security standards such as SPDM, DICE, TPM 2.0, and NIST SP 800-193; familiarity with Caliptra and OCP security specifications.
• Working knowledge of confidential computing: CPU TEEs (TDX, SEV-SNP, CCA), TDISP/TEE-IO, PCIe/CXL IDE, and memory encryption.
• Familiarity with PCIe Gen 5/6, CXL, SR-IOV, IOMMU, and secure virtualization mechanisms.
• Understanding of network and interconnect security (MACsec, IPsec, PSP, TLS) and the cost of line-rate encryption in high-bandwidth fabrics.
• Solid applied cryptography fundamentals (AES-GCM/XTS, SHA-2/3, ECDSA, key derivation) and awareness of post-quantum migration (ML-KEM, ML-DSA, LMS/XMSS for firmware signing).
• Experience with structured threat modeling and with side-channel and fault-injection analysis and countermeasures. Preferred Skills
• Experience taking products through FIPS 140-3, Common Criteria, or similar certification a plus.
• Experience securing datacenter accelerators, GPUs, DPUs, or BMC/OpenBMC firmware a plus.
• Experience with RISC-V security features (PMP/ePMP, WorldGuard), secure firmware in Rust or C, or SystemVerilog/formal security verification a plus. Contact: Uday Mulya Technologies [email protected] www.mulyatech.com

📌 Security Architect – Datacenter-Scale AI Inference (India)
🏢 EnCharge AI
📍 India