About the Company www.enchargeai.com

About the Role

FPGA Prototyping Engineer – AI Inference Systems Location: Remote : EnCharge AI is seeking an experienced FPGA Prototyping Engineer with deep expertise in multi-FPGA prototyping of large SoCs to help bring up the next-generation AI inference platform, from the accelerator SoC to multi-chip, rack-scale scale-up and scale-out systems. You will set the technical direction for, build, and own the FPGA prototypes that run our silicon designs at near-real-time speeds against real interfaces, giving firmware and software teams fast development platforms and giving the hardware team early proof that our systems work with real hosts, memory, and networks. This role focuses on RTL-to-FPGA porting of large AI accelerator SoCs and chiplet-based systems on Siemens Veloce proFPGA Uno, Quad and Hexa, including multi-FPGA partitioning, clock and memory remapping, and timing closure; daughter cards and real-interface bring-up for PCIe, HBM/DDR, Ethernet, and scale-up links; multi-chip prototypes of scale-up and scale-out systems; and delivering high-speed firmware and software development platforms.

You will define and drive the prototyping methodology for at-speed debug and build release, and carry prototype hardware and content into post-silicon bring-up.

Responsibilities

- Set the FPGA prototyping strategy for AI accelerator SoCs and multi-die/chiplet systems, and own the Veloce Primo and proFPGA prototyping environment end-to-end.
- Port ASIC RTL to FPGA: partition designs across multiple FPGAs, plan inter-FPGA connectivity and pin multiplexing, convert gated and generated clocks, and remap ASIC memories, PLLs, and hard macros to FPGA equivalents.
- Drive synthesis, place-and-route, and timing closure with AMD Vivado on large AMD FPGAs (e.g., Virtex UltraScale+ VU19P- and Versal Premium VP1902-class devices)



to reach target prototype frequencies and continuously improve build turnaround time.
- Select, integrate, and bring up daughter cards and real interfaces, including PCIe, HBM/DDR memory, Ethernet to real NICs and switches, and scale-up chip-to-chip links over FPGA transceivers.
- Build multi-chip prototypes that connect multiple accelerator instances over physical scale-up and scale-out links, to validate link training, fabric protocols, and system topologies before silicon.
- Deliver stable, high-speed prototype platforms to firmware, driver, and runtime teams for long-running software development, boot and OS bring-up, and interoperability testing at speeds emulation cannot reach.
- Define the at-speed debug methodology (embedded logic analyzers such as Vivado ILA, Veloce prototyping debug and trace capture, signal probing, and JTAG/UART access) and lead triage of hardware, board, and interface issues.
- Own prototype build and release management: track RTL drops, maintain FPGA-specific RTL changes, and automate builds, board health checks, and smoke tests.
- Provide technical leadership for prototyping across RTL design, verification, firmware, system software, and lab teams: define prototyping plans and milestones, mentor engineers within the prototyping team, and work with Siemens EDA and board vendors on capacity, tool, and hardware issues.
- Hand off to post-silicon by transitioning prototype test content, interface setups, and lab infrastructure to silicon bring-up, and help correlate silicon behavior with prototype results.




- Partner as a peer with the emulation team on shared RTL releases, and jointly decide which workloads run on prototypes versus emulation.

Qualifications

- BS/MS/Ph.D. in EE, CE, CS, or related field with deep FPGA implementation or FPGA prototyping experience on complex SoCs, including technical leadership of prototyping for at least one large SoC program.

Required Skills

- Deep hands-on experience with Siemens Veloce Primo and/or proFPGA, including multi-FPGA partitioning and prototype bring-up.
- Expert in FPGA synthesis, place-and-route, and timing closure with AMD Vivado on large, high-utilization AMD/Xilinx FPGAs.
- Solid SystemVerilog/Verilog skills, with experience adapting ASIC RTL for FPGA (clock conversion, memory remapping, multi-clock-domain designs).
- Experience bringing up high-speed interfaces on FPGA, such as PCIe Gen5/6, HBM/DDR, Ethernet, and multi-gigabit transceivers, including daughter card selection and integration.
- Comfortable in the lab with boards, cables, and instruments; experience with embedded debug (JTAG, GDB) and with firmware and Linux bring-up on prototypes.
- Strong scripting and automation skills in Python, Tcl, and shell for build and test automation.
- Proven ability to drive technical direction for prototyping across multiple teams.

Preferred Skills

- Experience with Synopsys HAPS or Cadence Protium a plus.
- Experience prototyping multi-chip systems, scale-up interconnects (e.g., UCIe, UALink), or scale-out networking (e.g., RoCE, Ultra Ethernet) a plus.
- Familiarity with AI/ML accelerators, RISC-V SoCs, or post-silicon validation a plus.
- We value demonstrated ability over years of experience; motivated, exceptional candidates at any career stage are encouraged to apply.

Contact

- Contact: Uday
- Mulya Technologies
- [email protected]
- www.mulyatech.com

📌 FPGA Prototyping Engineer – AI Inference Systems (India)
🏢 EnCharge AI
📍 India