About the Company
www.enchargeai.com

About the Role

Location:
Onsite/hybrid/Remote Emulation Engineer – AI Inference Systems

Location:
Onsite/Hybrid/Remote

Job Description
EnCharge AI is seeking an experienced Emulation Engineer with deep expertise in hardware emulation to help bring up the next-generation AI inference platform, from the accelerator SoC to multi-chip, rack-scale scale-up and scale-out systems. You will set the technical direction for, build, and own the pre-silicon environments that let hardware, firmware, and software teams run real inference workloads months before silicon arrives, and that de-risk tape-out at datacenter scale. This role focuses on emulation model build and partitioning of large AI accelerator SoCs and chiplet-based systems on Siemens Veloce, speed bridges and transactors for PCIe, LPDDR, HBM, Ethernet, and scale-up links, multi-chip and multi-node emulation of scale-up and scale-out fabrics, and pre-silicon bring-up of firmware, drivers, and the AI software stack. You will define and drive the emulation methodology for debug, power and performance analysis, and regression, and carry that infrastructure forward into post-silicon bring-up. Responsibilities
• Set the emulation strategy for AI accelerator SoCs and multi-die/chiplet systems, and own the Siemens Veloce emulation environment (Veloce Strato/Strato+ and Veloce CS) end-to-end.
• Build, compile, and partition multi-billion-gate designs across emulator boards and systems, managing clocking, memory modeling (HBM, DDR, on-chip SRAM), capacity, and compile turnaround time.
• Develop and integrate transactors for PCIe host interfaces, HBM, Ethernet, and die-to-die and chip-to-chip scale-up links (e.g., UCIe).
• Architect multi-chip and multi-node emulation configurations that model scale-up domains and scale-out fabrics, including collective communication traffic (e.g.,



all-reduce, all-to-all) across accelerators.
• Enable pre-silicon bring-up of boot ROM, firmware, kernel drivers, runtime, and compiler output, and run real inference models (e.g., LLMs and other transformer models) end-to-end on emulation with the ML software team.
• Perform power and performance analysis with Veloce Power App: capture switching activity on realistic workloads for power estimation and peak-power and di/dt analysis, and measure throughput, bandwidth, and latency to correlate against architectural performance models.
• Define the emulation debug methodology (full-visibility waveform and trace capture, triggers, assertions, transaction monitors, save/restore) and lead triage of the hardest issues spanning RTL, firmware, and software.
• Build and maintain regression infrastructure and automation that keeps emulation models current with RTL releases, integrates with CI, and maximizes emulator utilization and throughput.
• Provide technical leadership for emulation across architecture, RTL design, verification, firmware, and system software teams: define emulation plans, milestones, and tape-out readiness criteria, mentor engineers within the emulation team, and drive capacity planning and tool roadmap discussions with Siemens EDA.
• Partner as a peer with the FPGA prototyping team on shared RTL releases, and jointly decide which workloads run on emulation versus prototypes. Qualifications
• BS/MS/Ph.
D. in EE, CE, CS,



or related field with deep hardware emulation experience on complex SoCs, including technical leadership of emulation for at least one large SoC program through tape-out. Required Skills
• Deep hands-on experience with Siemens Veloce emulation (Veloce Strato/Strato+ or Veloce CS), including compile, partitioning, and runtime flows.
• Strong SystemVerilog/Verilog skills, with experience in emulation-friendly coding, design partitioning, and multi-clock-domain designs.
• Experience with transactor-based verification (e.g., AXI/PCIe transactors) for high-speed interfaces such as PCIe Gen5/6, HBM, and Ethernet.
• Strong scripting and automation skills in Python, Tcl, and shell, including regression management and CI systems.
• Proven ability to debug across the hardware/software boundary and to drive technical direction for emulation across multiple teams.
• Experience with emulation-based power analysis platforms a strong plus.
• Equivalent experience on Cadence Palladium or Synopsys ZeBu a plus.
• Experience with multi-chip/chiplet emulation, scale-up interconnects (e.g., UCIe, UALink), or scale-out networking (e.g., RoCE, Ultra Ethernet) a plus.
• Experience bringing up firmware, Linux drivers, or software stacks on emulation; proficiency in C/C++, Linux, and embedded debug (JTAG, GDB) a plus
• Familiarity with AI/ML accelerators, inference workloads, and frameworks such as PyTorch or ONNX Runtime a plus.
• We value demonstrated ability over years of experience; motivated, exceptional candidates at any career stage are encouraged to apply. Preferred Skills Not specified. Pay range and compensation package Not specified. Equal Prospect Statement Not specified. Contact
• Contact: Uday
• Mulya Technologies
• [email protected]
• www.mulyatech.com

📌 Emulation Engineer – AI Inference Systems (India)
🏢 EnCharge AI
📍 India