Location: Bangalore, Karnataka, India
Positions: 20
Employment: Full-time
Experience: 3–15 years
Candidates should have a clear understanding of BSCAN, MBIST, scan, ATPG, and simulation concepts. Experience in at least one of the following is required: MBIST insertion; scan insertion; ATPG pattern generation and simulation; or MBIST and BSCAN simulation using industry-standard Cadence, Siemens Tessent, or Synopsys tools.
Experience with zero-delay and SDF timing simulations is preferred. Solid debugging skills using GUI-based, industry-standard simulators such as VCS, NCSim, or Xcelium are required. Experience with fault models such as stuck-at, Transition Delay Faults (TDF), and IDDQ, as well as scan test coverage improvement techniques, is preferred.
Candidates should have SoC-level DFT experience, including OCC/OPCG insertion, EDT/compression logic insertion, and clock module handling for scan. Experience with post-silicon bring-up and/or production activities, including tester debugging using shmoo plots and graphs, is beneficial.
The role requires experience providing test-mode timing constraints to STA and PD teams. Strong communication and debugging skills are essential for cross-functional and customer-team collaboration, as well as leading and mentoring DFT engineers.