Job Description STA Engineer (Static Timing Analysis)

Job Title: STA Engineer Experience: 3–8 Years Domain: VLSI / Semiconductor Location: Bangalore / Noida

Key Responsibilities
Perform Static Timing Analysis (STA) at block and full-chip levels.
Analyze setup, hold, recovery and removal timing violations.
Develop, validate and debug timing constraints (SDC).
Perform timing analysis across multiple PVT corners and operating modes (MCMM).
Identify critical timing paths and recommend optimization solutions.
Work on timing closure in coordination with Physical Design and RTL teams.
Analyze timing reports and debug timing issues.
Perform pre-layout and post-layout timing analysis.
Ensure design meets timing requirements across all modes and corners.

Required Technical Skills
Solid understanding of Static Timing Analysis concepts.
Hands-on experience with Synopsys PrimeTime.




Positive knowledge of SDC constraints and timing exceptions.
Experience with setup/hold analysis and timing closure.
Knowledge of MCMM analysis and PVT corners.
Understanding of clock definitions, generated clocks, false paths and multicycle paths.
Basic TCL scripting skills.
Knowledge of signal integrity and crosstalk analysis is an added advantage.

Educational Qualification
B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI or related disciplines.

Preferred Candidate Profile
Strong debugging and analytical skills.
Hands-on experience in STA flows.
Positive understanding of digital design and physical design concepts.
Ability to collaborate with cross-functional VLSI teams.

📌 Sta Engineer Bengaluru
🏢 Mirafra
📍 Bengaluru