Your Role and Responsibilities:
Design and Develop communication interface between the Host and external devices for future technologies like PCI Gen6/7, CXL etc.
Modify/Develop how the host handles I/O protocols and all transactions coming from and going to I/O devices.
Design improvements to internal buffers and FSMs on Host bridge to handle increased bandwidth and latency requirements for current I/O technologies
Work closely with other interconnect teams and System design teams to define I/O Phy and interconnects for scalable systems

Required Education:

Bachelor's Degree

Preferred Education:

Master's Degree

Required Technical and Qualified Expertise:





Minimum 15 to 20 years of relevant experience with MS/PhD Hands-on RTL level experience of architecting and delivering industry standard IO interfaces Prior experience with PCIe Gen 5 or CXL Experience in working with architecture/ FW/ SW teams * Exposure to System architecture

Preferred Technical and Skilled Experience:
Specialized FPGA Knowledge: Experience with field-programmable gate array analysis and design, including use of design entry languages and design automation tools, is beneficial for driving innovation and efficiency in logic design.
Advanced Static Timing: Deep understanding of static timing and its application in chip logic development can be advantageous in driving business results.
Front-end Processing Expertise: Familiarity with front-end processing and its role in chip logic development can be valuable in shaping the future of cognitive systems logic design.

Years of Experience:15 - 20

📌 Io Architect Bengaluru
🏢 IBM
📍 Bengaluru