Principal Engineer – Design Verification | Bengaluru

Experience: 15+ years

We are hiring a Principal Engineer, Design Verification, to lead verification of high-performance networking silicon at our Bengaluru centre.

The role:
Own verification of critical networking IPs and large sub-systems, from test plan to coverage closure.
Architect UVM and SystemVerilog constrained-random settings from scratch.
Be the technical authority for complex, deep-seated hardware bugs.
Work with Design and Architecture teams to close ambiguities early in the design cycle.
Set code quality and reuse standards, and mentor the verification team.

Requirements:
15+ years in ASIC/SoC design verification with successful tape-outs.
Networking domain experience on high-throughput, data-intensive designs.
Expert-level SystemVerilog and UVM, including testbench and VIP integration from scratch.
IP and sub-system level verification leadership, with SoC integration exposure.
Added advantage: Formal Property Verification, Python or Perl automation.

If you are interested, DM your updated CV!

📌 Senior Design Verification Engineer Bangalore Metropolitan Area
🏢 Product Start- Up
📍 Bangalore Metropolitan Area