Hiring for DFT Verification Engineer

Job Description: DFT Verification Engineer:

5+ years of Verification experience

Robust knowledge of basic DFT features and IEEE standards including JTAG/iJTAG, MBIST,

Strong hands-on expertise in TestBench archtecture, C++, SystemVerilog, SVA and UVM

Experience with SoC/IP hierarchical verification, directed and constrained-random simulation/emulation environments, test planning, debugging and coverage closure

Scripting experience in Tcl, Perl or Python

Understanding of low-power verification, power gating, and UPF concepts

Goal oriented, self-starter, able to independently drive tasks to completion and work collaboratively across teams.

Preferred:

Experience with interrupt, DMA, security, and reset/power-gating UPF verification

Familiarity with AXI, APB, SPI, I2C, SDP, and PCIe protocols.

Experience with formal verification techniques and industry tools.

Education:

B.Tech/M.Tech in ECE, VLSI, Microelectronics, or related discipline.

? Interested candidates can share their updated resumes [email protected] or DM me for more details.

Regards,

Jaya

📌 Opening for DFT Verification Engineer - Bangalore/ Hyderabad (Bengaluru)
🏢 UST
📍 Bengaluru