Job Description
• Develop and execute pre-silicon verification test plans for DFT features of the chip. Develop directed and random verification tests to validate the functionality.
• Verify DFT design blocks and subsystems (such as MBIST, high speed IO PHY, fuse, clocks, reset) using complex SV or C++ verification environments. Construct SystemVerilog and/or C/C++ models and test sequence libraries for simulation.
• Build test bench components including agents, monitors, scoreboards for DUT. Compose tests, assertions, checkers, validation vectors and coverage bins to ensure verification completeness.
• Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives.
• Develop high coverage and cost effective test patterns, and take part in ATE bring-up.
• Post silicon ATE and System level debug support of the test patterns delivered. Optimize the test patterns to improve the test quality and reduce test costs. Preferred
Experience:
• 10+ year experience in DFT feature verification (such as JTAG, MBIST, SCAN, fuse, IO-PHY loopback testing)
• Strong background in Verilog, SystemVerilog (SV), SVA, UVM verification methodologies and C++
• Solid debug skills and experience with debug tools such as Verdi.
• Experience with EDA simulation tools like Synopsys VCS, Cadence NCSIM, Verdi
• Experience with scripting languages like Tcl/Perl/Ruby/Python
• Working knowledge of Unix/Linux OS, file version control. Additional
skills:
• Experience in ATE debug, Synthesis, formal/LEC, or power analysis will be a plus.
• Strong analytical/problem solving skills and pronounced attention to details.
• Knowledge of STA Constraints for various DFT modes.
• Excellent written and verbal communication Educational background:
• Minimum Engineering Degree in Electronics/Electrical/Computer Science.