Opening for Design Verification Verification Engineer with 4+ years of experience in functional verification Required
Skills:
• Robust proficiency in SystemVerilog (SV) and UVM
• Excellent debugging and problem-solving skills
• Experience in verification environment development, testbench architecture, and regression debugging Preferred
Skills:
• Knowledge of memory protocols such as LPDDR5, DDR5, and LPDDR6 will be an added advantage ? Interested candidates can share their updated resumes [email protected] or DM me for more details. Regards, Jaya