Job Requirements

- Minimum 8 years of experience with strong layout knowledge

- Bachelor's degree required.

- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).

- Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).

- Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.

- Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.

- Manage scheduling, timelines, and layout floor-planning.

- Responsible for start to end deliverables with quality within the planned schedule.

- Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.

- Able to think and help in layout scripting and automation

Skill Set (Memory)

- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna,



ElectroMigration) in CMOS processes.

- Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.

- Proficiency in floor-planning, hierarchy layout, and chip integration.

- Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines

- Knowledge of AI, automation in layout, Script Programming and SKILL Programming

- Ability to lead, train junior engineers, and manage projects effectively.

- Good knowledge of memory layout topology;

experience with memory compilers is a plus.

- Ability to lead recent technology reviews to document layout methodologies, flows, and guidelines.

- Self-reliant with the ability to work both independently and collaboratively.

R027716

📌 Sr. Memory Layout Design Engineer (Bengaluru)
🏢 Broadcom
📍 Bengaluru