- Proficient with Synopsys and Cadence tools for synthesis and STA
Job Overview Join our innovative team as a Senior Synthesis Static Timing Analysis Engineer, where you will lead the RTL-to-netlist implementation flow. Collaborate with diverse teams to deliver sign-off quality results for complex SoC/ASIC designs, leveraging advanced tools like Synopsys and Cadence. Your contributions will significantly impact our embedded engineering services in sectors such as automotive, industrial, and medical, all from our world-class facilities.
- Perform RTL synthesis using Synopsys and Cadence, optimizing for PPA.
- Develop and maintain timing constraints for synthesis and STA.
- Execute Static Timing Analysis at both block and top levels.
- Analyze and resolve timing violations and perform necessary ECOs.
- Collaborate with design teams to achieve timing closure and sign-off.
- Enhance flow methodologies across synthesis and STA stages.
Who you are
- Holder of a B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering.
- Proficient with Synopsys and Cadence tools for synthesis and STA.
- Skilled in scripting with TCL, Perl, and Python.
- Experienced with advanced process nodes (7nm/5nm/3nm).
- Solid analytical and collaborative skills for global teamwork.
Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.