We are looking for an experienced Physical Design Engineer with 10+ years of hands-on experience in ASIC and SoC physical design implementation.

The ideal candidate should have strong expertise in RTL-to-GDSII implementation, floorplanning, placement, clock tree synthesis, routing, timing closure, power optimisation and physical verification. The candidate will be responsible for implementing complex designs, resolving physical design challenges and ensuring successful tape-out within defined power, performance and area (PPA) targets.

Key Responsibilities

- Own and execute end-to-end physical design implementation from netlist handoff to GDSII.
- Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing and physical design closure.
- Drive timing closure across pre-CTS, post-CTS and post-route stages.
- Analyse and resolve setup and hold violations, congestion, signal integrity and design rule violations.
- Perform power, performance and area (PPA) optimisation to meet design specifications.
- Work on multi-mode, multi-corner (MMMC) timing analysis and optimisation.
- Collaborate with RTL Design, Design Verification, DFT, STA and Physical Verification teams.
- Perform physical design optimisation, including buffering, cell sizing, placement optimisation and routing refinement.
- Analyse and resolve issues related to IR drop, electromigration (EM), crosstalk and signal integrity.
- Ensure design quality through physical verification checks such as DRC, LVS and antenna checks.
- Review timing reports, congestion reports, placement quality and routing results.
- Develop and optimise physical design flows, methodologies and automation scripts.
- Participate in design reviews, technical discussions and tape-out readiness activities.
- Mentor junior engineers and provide technical guidance wherever required.

Mandatory Technical Skills





- 10+ years of experience in Physical Design implementation for ASIC / SoC designs.
- Solid understanding of the complete RTL-to-GDSII flow.
- Hands-on expertise in:
- Floorplanning and power planning.
- Placement and optimisation.
- Clock Tree Synthesis (CTS).
- Global and detailed routing.
- Static Timing Analysis (STA) and timing closure.
- Setup and hold violation analysis and fixing.
- Congestion analysis and optimisation.
- Power, Performance and Area (PPA) optimisation.
- Strong understanding of multi-mode, multi-corner (MMMC) implementation.
- Knowledge of signal integrity, crosstalk, IR drop and electromigration.
- Experience with physical verification, including DRC, LVS and antenna checks.
- Good understanding of semiconductor technology, standard cells, libraries and timing constraints.
- Ability to analyse complex design issues and drive solutions independently.

EDA Tools Hands-on experience with one or more of the following industry-standard tools:

- Synopsys ICC2 / IC Compiler.
- Cadence Innovus.
- Synopsys PrimeTime.
- Cadence Tempus.
- Synopsys Fusion Compiler.
- Synopsys StarRC.
- Cadence Quantus.
- RedHawk / Voltus for power integrity analysis.

Scripting and Automation

- Experience with Tcl scripting for physical design automation.
- Knowledge of Python, Perl or Shell scripting.
- Ability to automate repetitive tasks, analyse reports and improve implementation efficiency.

Good to Have Skills

- Experience in advanced technology nodes such as 7nm, 5nm, 3nm or below.
- Experience with high-performance computing, networking, automotive or mobile SoCs.
- Exposure to hierarchical physical design and large block-level implementation.
- Experience with low-power design techniques and power intent (UPF).
- Knowledge of ECO implementation and engineering change order flows.
- Experience in physical design methodology development and flow optimisation.
- Exposure to chiplet-based architectures and advanced packaging.

📌 Senior Physical Design Engineer (ASIC / SoC / VLSI) (Bengaluru)
🏢 Hucon Solutions
📍 Bengaluru