Job Summary

We are looking for an experienced GLS Verification Engineer with 6+ years of hands-on experience in Gate-Level Simulation (GLS) and ASIC/SoC verification.

The ideal candidate should have strong expertise in gate-level simulation, post-synthesis and post-layout verification, timing-aware simulation, SDF annotation, X-propagation analysis and debugging. The candidate will be responsible for validating gate-level netlists, identifying functional and timing-related issues, and ensuring design readiness for silicon tape-out.

Key Responsibilities

- Drive gate-level simulation and verification activities for complex ASIC and SoC designs.
- Perform GLS at different stages of the design flow, including post-synthesis and post-physical design.
- Develop and execute GLS test plans and simulation scenarios based on design specifications.
- Perform zero-delay and timing-annotated simulations using SDF (Standard Delay Format).
- Analyse and debug functional mismatches between RTL and gate-level simulations.
- Identify and resolve X-propagation issues, timing violations and race conditions.
- Perform reset and clock sequencing checks, including asynchronous reset behaviour.
- Debug setup and hold-related simulation failures and timing-related functional issues.
- Work closely with RTL Design, Design Verification, STA, DFT and Physical Design teams to resolve design issues.
- Analyse simulation logs, waveforms and timing reports to identify root causes.
- Develop and maintain GLS regression environments and automation scripts.
- Ensure adequate simulation coverage for critical design scenarios.
- Support post-synthesis and post-layout verification sign-off activities.
- Participate in design reviews, verification closure and tape-out readiness assessments.

Mandatory Technical Skills

- 6+ years of experience in ASIC / SoC verification, with strong hands-on expertise in Gate-Level Simulation.




- Strong understanding of GLS methodologies and gate-level netlist verification.
- Excellent knowledge of Verilog and SystemVerilog.
- Hands-on experience with SDF annotation and timing-aware GLS.
- Experience in post-synthesis and post-layout gate-level simulations.
- Strong understanding of X-propagation, unknown-state analysis and debugging.
- Experience in debugging RTL versus gate-level simulation mismatches.
- Understanding of setup and hold timing, clock domains, reset synchronisation and timing checks.
- Knowledge of SDF back-annotation, specify blocks and timing checks.
- Robust debugging skills using simulation logs, waveforms and relevant reports.
- Understanding of ASIC/SoC design flow, synthesis and physical design processes.

EDA Tools Experience with one or more of the following tools:

- Synopsys VCS
- Cadence Xcelium
- Siemens Questa / ModelSim
- Synopsys Verdi
- Cadence SimVision
- Synopsys Design Compiler
- Cadence Genus

Scripting and Automation

- Good experience with Shell scripting.
- Working knowledge of Python, Perl or Tcl.
- Ability to automate GLS regression execution, log analysis and failure reporting.
- Experience in developing scripts to improve simulation and debugging efficiency.

Good to Have Skills

- Experience in low-power GLS and UPF-based verification.
- Knowledge of power-aware simulation and isolation/retention cell behaviour.
- Exposure to scan-enabled and DFT-related gate-level simulations.
- Experience with post-route GLS and timing-annotated netlists.
- Knowledge of SDC constraints and Static Timing Analysis (STA).
- Exposure to multi-clock and multi-reset domain designs.
- Experience with emulation or hardware-assisted verification.
- Understanding of ECO verification and post-ECO simulation.

Education Bachelor's or Master's degree in Electronics and Communication Engineering, Electrical Engineering, VLSI or a related discipline.

📌 Senior GLS Verification Engineer (ASIC / SoC) (Bengaluru)
🏢 Hucon Solutions
📍 Bengaluru