Senior Design Verification Engineer

Requirements

- Electronic Engineering/Computer Engineering degree with 5-8 years of progressive experience in digital design and verification.

- Must have demonstrated experience in developing UVM-based testbench infrastructure from ground up, functional cover point development, functional & code coverage analysis/closure and assertion development.

- Experience on both IP and SoC level verification with working knowledge of gate level simulations.

- Knowledge in AHB/AXI/APB protocols is desirable;

Experience in Power aware simulations or Formal Verification is a big plus.

- Proficiency in Scripting languages and utilities including Makefile, Python, Perl etc.

- Must be a self-starter, should be able to work on assignments with minimal directions.

- Experience collaborating with product development groups spread across the globe is a must; should have solid interpersonal and communication skills.

Responsibilities





- Verification of key digital blocks in differentiated mixed signal SOCs targeted for the consumer market

- Complete verification ownership Testbench Architecture, Testplan and Testbench Development, Functional Coverage Closure and Code Coverage Closure

- Usage of industry standard methodologies like UVM and constrained random approach to achieve verification goals

- Actively explore and deploy ML techniques to achieve faster turnaround time

- Debug efficiently and clearly articulate gating issues to engineering leads.

- Integrate the block level testbench at SOC level and verify SOC integration

- Involvement in post-silicon activities such as silicon bring-up, evaluation support, ATE pattern bring-up to take SoC into production.

Additional Qualifications & Experience:

- Digital Signal Processing concepts, and tools such as MATLAB or Octave

- Experience with HW emulation or FPGA prototyping is a plus

📌 Senior Engineer, Design Verification Engineering (Hyderabad)
🏢 Analog Devices
📍 Hyderabad