We are looking for experienced Analog Layout Engineers with robust hands-on experience in custom analog layout design using advanced TSMC technology nodes.
Key Responsibilities
- Develop and implement custom analog and mixed-signal layouts.
- Work on advanced technology nodes, preferably TSMC 7nm, 5nm, 3nm or below.
- Handle block-level and full-chip analog layout implementation.
- Perform floorplanning, placement, routing and device matching.
- Ensure high-quality layout implementation considering area, power and performance.
- Perform DRC, LVS, ERC and physical verification.
- Handle parasitic extraction and post-layout verification.
- Work closely with Analog Design,
Circuit Design and Physical Verification teams.
Required Skills
- 5+ years of experience in Analog Layout Design.
- Strong hands-on experience in TSMC advanced technology nodes (7nm/5nm/3nm/2nm).
- Good understanding of CMOS layout concepts and transistor-level layout.
- Hands-on experience with Cadence Virtuoso.
- Strong knowledge of DRC, LVS, ERC and physical verification.
- Experience in matching techniques, common-centroid, guard rings and shielding.
- Knowledge of parasitic extraction and post-layout analysis.
- Experience in analog and mixed-signal layout implementation.