We are actively hiring ASIC RTL Design Engineers to join our growing semiconductor team. This role offers an opportunity to work on next-generation RTL design, integration, Quality checks, validation, and performance optimization.
Key Responsibilities
- Develop and maintain RTL using Verilog/SystemVerilog/VHDL.
- Resolve synthesis, timing, CDC, and functional issues.
- Debugging, and system validation. .
- Participate in SoC integration, IP development, and subsystem design.
- Collaborate with verification, physical design, and architecture teams.
Mandatory Skills
- Robust RTL Design experience using Verilog/SystemVerilog/VHDL
- Hands-on experience with SpyGlass Lint & CDC
- Strong understanding of Micro-architecture and SoC Design
- Experience with ASIC Synthesis, STA, and Timing Closure
- SoC Integration and IP Development
- AMBA protocols: AXI, AHB, APB
Preferred Skills
- Scripting: Python, Perl, TCL, Makefile
- Knowledge of Computer Architecture
- Experience with one or more protocols:
- PCIe
- Ethernet
- DDR
- USB
- MIPI
- UART
- SPI
- I2C
- Experience working on processor-based systems
- Exposure to complex SoC/IP development projects