Job highlights

- Bachelor s or Master s degree in Electrical / Electronics/VLSI Engineering or equivalent

- Required Qualifications
- 10+ years proven hands-on experience in DFT for digital ASIC / SoC development,with multiple tapeouts for large designs
- Experience with DFT for advanced nodes ( 7nm),5D / 3D packaging,or high-speed IP
- Own and drive all aspects of DFT architecture, definition, and implementation for digital chips, including scan insertion, ATPG, boundary scan, MBIST, logic BIST, JTAG and test compression techniques.
- Hands-on execution with EDA tools for scan synthesis, test pattern generation, fault simulation, and DFT rule checks.
- Create and validate test plans targeting high coverage for stuck-at, transition, and critical path faults.
- Integrate DFT with RTL and physical design teams; resolve complex trade-offs impacting fault coverage, PPA, or manufacturability.
- Optimize test modes, design for manufacturability, and debug silicon failures from bring-up through production ramp.
- Develop and implement low-overhead test structures and warranty schemes for current and legacy IP.
- Directly debug, analyze, and resolve DFT-related issues in simulation, emulation, and in the lab using standard test equipment.
- Deliver documented DFT architectures, test strategies, implementation scripts (TCL/Python/Perl), and design guidelines for engineering teams.




- Collaborate with ATE test engineers to implement production test solutions, reduce test costs, and improve coverage.
- Mentor engineers in DFT methodology, best practices, tool usage, and industry standards.

Required Qualifications

- Bachelor s or Master s degree in Electrical/Electronics/VLSI Engineering or equivalent.
- 10+ years proven hands-on experience in DFT for digital ASIC/SoC development, with multiple tapeouts for large designs.
- Expert skills in DFT flows: scan, ATPG, MBIST, BIST, JTAG, boundary scan, fault simulation.
- Strong command of EDA tools: Synopsys DFT Compiler, Tessent, Cadence Modus, or equivalent.
- Scripting abilities (TCL, Python, Perl) for DFT automation and reporting.
- Solid knowledge of RTL design, synthesis, timing, and SoC architecture constraints.
- Demonstrated ability to debug complex DFT and test-mode issues at lab and production level.
- Ability to create technical documentation, guides, and mentor junior engineers.

Nice-to-Have Skills

- Experience with DFT for advanced nodes ( 7nm), 2.5D/3D packaging, or high-speed IP.
- Production ATE pattern development and test data evaluation.
- Knowledge of safety (ISO 26262) or security-oriented DFT requirements.
- DFT for memory BIST (SRAM/DRAM), and custom macro testing.

📌 Principal DFT Engineer (Bengaluru)
🏢 Analog Devices
📍 Bengaluru