Hiring Now: Senior STA/SDC Lead | Bangalore | 12 Years
We are looking for an experienced Senior STA/SDC Lead to join a high-impact semiconductor program working on advanced technology nodes.
Location: Bangalore
Experience: 12 Years
Open Positions: 2
Immediate / Early Joiners Preferred
Key Responsibilities
- Lead end-to-end Static Timing Analysis (STA) and timing signoff activities for complex SoCs, Subsystems, and IPs.
- Own SDC development, constraint validation, MMMC setup, timing closure, and signoff delivery across all modes and corners.
- Drive timing convergence through collaboration with RTL, Synthesis, Physical Design, DFT, and Architecture teams.
- Define and review clocking strategies, timing exceptions, generated clocks, false paths, multicycle paths, and signoff methodologies.
- Lead customer discussions, mentor engineers, and drive successful tapeout execution.
Must-Have Skills
Full-Chip STA Signoff
Advanced SDC Expertise
Synopsys PrimeTime / PrimeTime-SI
Cadence Tempus
MMMC Setup & Timing Closure
ECO Signoff
OCV / AOCV / POCV / CRPR
Crosstalk & Signal Integrity Analysis
Low-Power Timing Verification
Tcl Scripting
Advanced Node Experience (2nm / 3nm / 5nm)
RTL-to-GDSII Flow Understanding
Customer-Facing & Technical Leadership Experience
Positive to Have
- Python / Perl / Shell Scripting
- Automation and Productivity Enhancement Development
- Team Mentoring and Stakeholder Management
Interested candidates can share their updated resumes to [HIDDEN TEXT]