We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.
Position: Sr Formal Verification Engineer
Experience: 8+ Years
Location: Bengaluru
Contract Period: 12 months
We are looking for an experienced Formal Verification Engineer with strong expertise in SystemVerilog Assertions (SVA), Formal Property Verification, and formal verification methodologies. The candidate will work on Test Chip connectivity verification and DDRPHY block-level property verification.
Key Responsibilities
- Develop and verify SystemVerilog Assertions (SVA).
- Perform Formal Property Verification (FPV) for DDRPHY and Test Chip designs.
- Handle connectivity verification for Test Chips.
- Develop abstract models and formal verification infrastructure.
- Work on FPV, DPV, SEQ, and other formal verification methodologies.
- Manage formal regressions and support verification activities.
- Contribute to test plan development and formal signoff.
Mandatory Skills
- Solid hands-on experience in SystemVerilog Assertions (SVA).
- In-depth knowledge of Formal Verification algorithms, engines, and methodologies.
- Experience with Formal Property Verification (FPV).
- Understanding of formal convergence techniques and signoff.
- Experience in abstract model development.