Job highlights

- 5-9 years experience in ASIC Design Verification with strong SystemVerilog and UVM skills, expertise in AMBA protocols and high-speed interfaces like Ethernet and PCIe
- Develop and execute IP, subsystem, and SoC verification plans; build UVM testbenches; drive verification closure; debug design issues; mentor juniors; develop automated verification flows

About the Role We are looking for an ASIC Design Verification Engineer to join the Infrastructure organization. The role involves building IP and System-on-Chip (SoC) solutions for data center applications. You will be responsible for verification closure of design modules and subsystems, including test planning, UVM-based testbench development, simulation, formal verification, and emulation.

You will collaborate with ASIC Design, Software, Hardware, Emulation, and Post-Silicon teams to ensure first-pass silicon success.

Key Responsibilities

- Develop and execute IP, subsystem, and SoC verification plans.
- Build UVM-based verification environments and functional test cases.
- Drive verification closure using functional and code coverage metrics.
- Debug and resolve design issues in collaboration with design teams.
- Perform functional, performance, and compliance testing.
- Work closely with Design, Emulation, Silicon Validation, and Modeling teams.
- Mentor junior verification engineers and contribute to verification methodology improvements.




- Develop automated verification flows and infrastructure.

Mandatory Skills

- 5 to 9 years of experience in ASIC Design Verification.
- Strong expertise in SystemVerilog and UVM methodology.
- Experience with Verilog, C/C++, and Python-based verification.
- Strong understanding of AMBA protocols (AXI/APB).
- Hands-on experience with Ethernet, PCIe, RDMA, or other high-speed protocols.
- Experience in IP, Cluster, and SoC-level verification.
- Experience with RTL and Gate-Level Verification.
- Strong debugging and root cause analysis skills.
- Experience in UVM-based verification setting development from scratch.
- Knowledge of scripting languages such as Python, Perl, or TCL.
- Experience with verification tools, waveform debugging, and simulators.
- Experience using Git, Mercurial (Hg), or SVN.
- Strong understanding of networking and data center applications.

Preferred Skills

- Experience with DDR, HBM, ARM, RISC-V, and 400G MAC verification.
- Knowledge of Formal Verification, SystemVerilog Assertions (SVA), and Emulation.
- Experience in AI/ML, Networking, or Video ASIC verification.
- Experience with automated verification flows and performance analysis.
- Strong collaboration skills across Design, Emulation, and Silicon Validation teams.

Educational Qualification

- Bachelor's Degree in Computer Science, Computer Engineering, or a related technical field (or equivalent practical experience).

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