- Responsible for DFT architecture and implementation.
- Perform scan insertion and scan chain implementation.
- Work on ATPG pattern generation and fault coverage analysis.
- Debug scan-related issues and ensure DFT quality.
- Collaborate with RTL, Physical Design and Verification teams.
Preferred Candidate Profile
- 5 years of experience in DFT engineering.
- Minimum 6 months of hands-on Scan Insertion experience.
- Strong understanding of DFT concepts and scan architecture.
- Knowledge of ATPG, Scan Compression and JTAG.
- Experience in ASIC/SoC design flows.
- Positive debugging and problem-solving skills.
- Willingness to work from Bangalore.
Role: Hardware Platform Engineer, Industry Type: Recruitment / Staffing, Department: Engineering - Hardware & Networks, Employment Type: Full Time, Temporary/Contractual Role Category: Hardware Education UG: Any Graduate Key Skills Skills highlighted with ‘‘ are preferred keyskills DFTScan InsertionScan ChainATPGScan Compression Design for TestabilityJTAGFault Coverage AnalysisDFT ImplementationASICSoC DesignDFT Verification.