Job highlights

- Experience: 5-8 years in DFT Engineer role with ATPG experience (Must). . Disclaimer: This job posting has been aggregated from external source
- Required Skills: ASIC / SoC design flow,Scan / ATPG,MBIST / LBIST,JTAG,Synopsys / Cadence/Mentor DFT tools,Verilog / SystemVerilog,fault simulation

DFT (Design for Testability) Engineer DFT (Design for Testability) Engineer
- Bangalore, Karnataka

DFT (Design for Testability) Engineer Role Summary: We are seeking a DFT Engineer to design and implement testability structures for complex ASIC/SoC designs, ensuring high test coverage, manufacturing yield, and silicon quality across advanced technology nodes.

Responsibilities

Implement scan insertion, ATPG pattern generation, and fault coverage analysis for digital designs

Design and integrate Memory BIST (MBIST) and Logic BIST (LBIST) architectures

Develop and validate JTAG/boundary scan (IEEE 1149.1) implementations





Collaborate with RTL design teams to ensure DFT-friendly design practices are followed early in the design cycle

Analyze test coverage reports and work to close coverage gaps

Support silicon bring-up and debug using DFT structures for yield analysis

Work with EDA tools (Synopsys TestMAX/DFTMAX, Cadence Modus, Mentor Tessent) for ATPG and BIST implementation

Coordinate with foundry/test teams on ATE (Automated Test Equipment) pattern conversion and correlation

Required Skills: ASIC/SoC design flow, Scan/ATPG, MBIST/LBIST, JTAG, Synopsys/Cadence/Mentor DFT tools, Verilog/SystemVerilog, fault simulation

Experience: 5-8 years in DFT Engineer role with ATPG experience (Must).

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 DFT ( Design For Testability ) Engineer (Bengaluru)
🏢 Central Business Solutions
📍 Bengaluru