Design Verification Engineer - Bangalore / Hyderabad (Bengaluru)

13 Nov

UST

Bengaluru

13 Nov

UST

Bengaluru

Opening for Design Verification

Verification Engineer with 4+ years of experience in functional verification

Required Skills

- Solid proficiency in SystemVerilog (SV) and UVM
- Excellent debugging and problem-solving skills
- Experience in verification environment development, testbench architecture, and regression debugging

Preferred Skills

- Knowledge of memory protocols such as LPDDR5, DDR5, and LPDDR6 will be an added advantage

? Interested candidates can share their updated resumes [email protected] or DM me for more details.

Regards,

Jaya

📌 Design Verification Engineer - Bangalore / Hyderabad (Bengaluru)
🏢 UST
📍 Bengaluru

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