Job Summary

We are looking for an experienced Design Verification Lead with 10+ years of experience in SoC and ASIC verification to lead the verification strategy, planning and execution for complex semiconductor designs.

The ideal candidate should have strong expertise in SystemVerilog, UVM, functional verification, constrained-random testing, coverage-driven verification and debugging. The candidate will be responsible for leading a team of verification engineers, ensuring verification quality and driving projects towards successful tape-out.

Key Responsibilities

- Lead the end-to-end design verification activities for complex IPs, subsystems and SoC-level designs.
- Define verification strategies, test plans, verification methodologies and schedules based on design specifications.
- Develop and review SystemVerilog/UVM-based testbenches, test scenarios, sequences and verification components.
- Drive constrained-random verification, assertion-based verification and functional coverage closure.
- Own verification planning, execution, debugging and sign-off activities.
- Analyse functional coverage, code coverage and regression results to identify verification gaps.
- Collaborate closely with RTL Design, Architecture, DFT, Physical Design and other cross-functional teams.
- Lead debug activities involving simulation failures, waveform analysis and root-cause identification.
- Drive regression management, automation and verification environment optimisation.
- Mentor and guide verification engineers, conduct technical reviews and ensure adherence to verification best practices.
- Track project milestones, identify risks and ensure timely delivery of verification objectives.
- Participate in design reviews, specification reviews and tape-out readiness assessments.

Mandatory Technical Skills





- Strong hands-on experience in Digital Design Verification for ASIC / SoC / IP-level designs.
- Excellent knowledge of SystemVerilog and UVM.
- Experience in developing UVM testbenches, agents, drivers, monitors, scoreboards and sequences.
- Strong understanding of constrained-random verification and functional coverage.
- Experience with SystemVerilog Assertions (SVA) and assertion-based verification.
- Expertise in simulation, debugging and waveform analysis.
- Experience with industry-standard EDA simulation tools such as Synopsys VCS, Cadence Xcelium or Siemens Questa.
- Good understanding of digital design concepts, RTL and Verilog.
- Experience in functional coverage closure, code coverage analysis and regression management.
- Strong problem-solving, debugging and analytical skills.

Leadership and Management Skills

- Proven experience leading and mentoring a team of Design Verification Engineers.
- Ability to define verification strategies and drive execution independently.
- Experience in task allocation, effort estimation, schedule tracking and technical reviews.
- Ability to work closely with architecture, RTL design and cross-functional engineering teams.
- Strong communication, stakeholder management and technical decision-making skills.

Valuable to Have Skills

- Experience in subsystem-level and full-chip SoC verification.
- Knowledge of AMBA protocols such as AXI, AHB and APB.
- Experience with PCIe, DDR, USB, Ethernet, MIPI or other high-speed interfaces.
- Exposure to low-power verification methodologies such as UPF.
- Knowledge of formal verification concepts and tools.
- Experience with scripting languages such as Python, Perl or Tcl.
- Exposure to emulation and hardware-assisted verification.
- Experience in processor-based SoC verification and complex bus/interconnect architectures.

Education

- Bachelor's or Master's degree in Electronics and Communication Engineering, Electrical Engineering, VLSI or a related discipline.

📌 Design Verification Lead (SoC / VLSI) (Bengaluru)
🏢 Hucon Solutions
📍 Bengaluru