As a DFT Architect/Manager/Sr. Manager at Velaura AI, you will lead the definition, implementation, and execution of Design-for-Test strategies for next-generation AI and high-performance computing silicon. You will be responsible for driving test architecture, methodology, and implementation across complex ASIC/SoC designs, ensuring high test quality, manufacturability, reliability, and production readiness. You will work closely with architecture, RTL, verification, physical design, STA, validation, product engineering, and manufacturing teams to integrate robust DFT features into the silicon platform. This is a highly visible technical and leadership role where you will influence DFT architecture, lead complex execution across teams, drive methodology improvements, mentor engineers, and support successful silicon bring-up, yield ramp, and production quality.