Roles & Responsibilities :- Own the complete FPGA flow from RTL adaptation to synthesis, implementation and bit-file generation.- Perform FPGA synthesis using Synplify Pro and place-and-route using Xilinx Vivado.- Adapt ASIC RTL code for FPGA implementation by replacing or modifying incompatible design blocks.- Develop and analyze FPGA-specific timing constraints and timing reports.- Identify and resolve timing issues, clock domain crossing (CDC), clock generation and combinatorial loop issues.- Develop VHDL, Verilog and SystemVerilog code for FPGA design and validation.- Write C-based test cases and Python scripts for FPGA testing and automation.- Perform FPGA device-level and board-level debugging.- Conduct bench-level electrical validation using oscilloscopes and digital analyzers.- Identify root causes of hardware and electrical issues.- Use revision control tools such as SVN and manage compute jobs.Preferred Candidate Profile :- 8 - 10 years of experience in FPGA design and validation.- Mandatory hands-on experience with Synplify Pro synthesis tool.- Solid experience with Xilinx FPGAs and Vivado place-and-route tools.- Expertise in complete FPGA development flow, from RTL to electrical validation.- Strong programming knowledge in VHDL, Verilog and SystemVerilog.- Experience adapting ASIC RTL for FPGA implementation.- Good understanding of timing constraints, timing analysis, CDC and clock generation.- Experience in Python and C-based test development.- Hands-on experience in device debugging and board-level debugging.- Strong knowledge of electronics fundamentals and bench-level validation.- Experience using oscilloscopes and digital analyzers.- Familiarity with SVN and revision control tools.- Willingness to work on-site at least 3 days per week. (ref:hirist.tech)

📌 FPGA Design & Validation Engineer (Bengaluru)
🏢 Allegis Global Solutions India Private
📍 Bengaluru