- Experience in coding RTL blocks and / or algorithms for ASICs in Verilog / SV is mandatory
- Experience in converting Micro-architecture to synthesizable RTL code keeping in mind area,latency and power constraints is needed . .
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- Experience in coding RTL blocks and/or algorithms for ASICs in Verilog/SV is mandatory (Pls note - we DO NOT want RTL INTEGRATION engineer profiles here)
- Experience in converting Micro-architecture to synthesizable RTL code keeping in mind area, latency and power constraints is needed
- Experience in running QC checks (CDC, Lint, X-prop) on the design and cleaning up design issues is mandatory
- FPGA RTL projects/profiles will be discounted from total experience/rejected
- Synthesis and constraint writing experience is valuable to have, but not mandatory