- . One or two FPGA RTL projects are OK,but the remaining projects must be ASIC RTL projects
- Experience in coding RTL blocks and / or algorithms for ASICs in Verilog / SV in at least 2 projects is mandatory
- Experience in running QC checks (CDC,Lint,X-prop) on the design and cleaning up design issues is mandatory
Experience - 5- 10 years
- Experience in coding RTL blocks and/or algorithms for ASICs in Verilog/SV in at least 2 projects is mandatory. This candidate could also have worked on a few RTL integration projects, but at least 2 RTL development (coding) projects are needed.
- Experience in running QC checks (CDC, Lint, X-prop) on the design and cleaning up design issues is mandatory
- One or two FPGA RTL projects are OK, but the remaining projects must be ASIC RTL projects
- Synthesis and constraint writing experience is valuable to have, but not mandatory