Physical Design Engineers & Analog Layout Engineers! (Bengaluru)

Physical Design Engineers & Analog Layout Engineers! (Bengaluru)

14 Nov
|
UST
|
Bengaluru

14 Nov

UST

Bengaluru

? We're Hiring: Physical Design Engineers & Analog Layout Engineers! ?

We are looking for talented and passionate VLSI professionals to join our growing team.

Open Positions

✅ Physical Design Engineer

✅ Analog Layout Engineer

Required Skills

Physical Design Engineer

?Floor Planning, Placement & Routing

?Clock Tree Synthesis (CTS)

?Timing Closure and STA

?IR Drop, EM Analysis

?Hands-on experience with industry-standard EDA tools

?Experience with advanced/lower technology nodes is highly preferred

Analog Layout Engineer

? Experience with Cadence Virtuoso Layout Suite

? Solid understanding of CMOS process technologies

? Knowledge of analog layout techniques, matching, shielding, and routing practices

? Hands-on experience with DRC, LVS, ERC, and PEX verification flows

? Hands-on experience with lower technology nodes (2nm,3nm)

Experience: 3 to 5 yrs

Location: Bangalore

Notice Period: Immediate to 30 Days Preferred

If you are interested or know someone who would be a great fit, please share your resume at [email protected] or send me a direct message.

Regards,

Jaya

📌 Physical Design Engineers & Analog Layout Engineers! (Bengaluru)
🏢 UST
📍 Bengaluru

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