Memory Layout design Engineers (New Delhi)

Memory Layout design Engineers (New Delhi)

14 Nov
|
Zia Semiconductor
|
New Delhi

14 Nov

Zia Semiconductor

New Delhi

Memory Layout design Engineers Experience : 2-5 Years Experience

Understanding of memory compiler floor plan Memory Leafcell layout development Memory backend Qualifications (DRC/ LVS/ ERC/ DFM) Electrical qualifications (EM/ IR)

📌 Memory Layout design Engineers (New Delhi)
🏢 Zia Semiconductor
📍 New Delhi

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