- Analyze DFT timings violations along with STA teams. . Requirement . Valuable experience in EDA tools : Synopsys Design Compiler and Tetramax (or similar tools)
* :- Co-work with Smartphone SOC team to plan modem DFT requirements. Handle pre-silicon DFT verification and post-silicon DFT related affairs. Doing scan synthesis and scan-chain analysis/stitching. Doing DCT/DCG synthesis. Memory macro replacement and MBIST generation. Prepare DFT timing constraints. Analyze DFT timings violations along with STA teams.
Requirement
Good experience in EDA tools : Synopsys Design Compiler and Tetramax (or similar tools) . Understanding DFT requirements for lower technology nodes. Ability to communicate effectively with multiple global cross-functional teams. Enthusiastic and ability to be an independent player and also work in teams.