We are looking for experienced RTL Design Engineers with robust expertise in end-to-end RTL development, from architecture and microarchitecture definition to complete RTL implementation.
Key Skills & Responsibilities:
Experience in architecture and microarchitecture development.
Solid hands-on experience in RTL design and implementation.
Expertise in converting design specifications into synthesizable RTL.
Proficiency in Verilog/SystemVerilog and RTL coding guidelines.
Understanding of lint, CDC, synthesis, and timing concepts.
Ability to independently drive RTL design and debugging.