Digital Validation: 8 to 10 years’ experience in FPGA design and validation Profile
• Experience in FPGA flow to take the design, adapt it and generate FPGA bit files. Masters the full FPGA flow from RTL to electrical validation
• Understands and develops timing constraints specific to FPGA and analyses timing reports for the given design in consultation with design team.
• Proven experience in digital design concepts and code development in VHDL/Verilog/system Verilog.
• Experience in adapting ASIC RTL code and replace blocks required to be able to fit it in an FPGA
• Positive understanding of timing issues in FPGA flow and how to address them, including clock domain crossings, clock generation, combinatorial loops.
• Proven experience with synplify synthesis tool,



Vivado place and route tool, Xilinx FPGAs
• Experience in writing C based tests for the FPGA testing.
• Experience in Python based code development.
• Experience in debug tools associated with FPGA debug.
• Robust experience in electronics fundamentals and debug.
• Ability to perform Device debug / Board debug and identify root cause, within an electrical validation setting.
• Need to be thorough at bench level validation Oscilloscope and digital analyzers.
• Familiar with revision control tools (SVN, run compute jobs)

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